Sr Staff Digital Verification Engineer
On-site · Shanghai, Shanghai, China
Job Summary
Senior Staff Digital Verification Engineer responsible for understanding the expected functionality of designs, designing and developing verification environments, improving verification architecture and flow, running RTL and gate-level simulations/regression, and developing code/functional coverage with analysis and closure. Requires MS in CS/ME, minimum 8 years of experience, proficiency in SystemVerilog/UVM, familiarity with ASIC design/verification tools, basic computer architecture, strong IC verification skills, and scripting in Python; familiarity with C/C++/Python and knowledge of USB, I3C, DDR protocol and mixed-signal verification are pluses. Remote work option available elsewhere; local Shanghai offices in-person opportunities.
Required Qualifications
- MS in CS/ME
- Minimum of 8 years' experience
- Proficiency in SystemVerilog and UVM
- Familiarity with ASIC design and verification tools and flow
- Familiarity with basic computer architecture
- Strong IC verification skills
- Good communication and problem solving skills
- Scripting and automation skills (Python)
- Familiar with C/C++/Python or other OO languages
- Knowledge of USB, I3C, DDR protocol is a plus
- Knowledge of Mixed signal verification is a plus
- Experience with setup over 100K lines verification environment
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