Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
$160,000–$220,000 year
On-site · Austin, Texas, United States or Irvine, California, United States
Job Summary
Senior-level SOC/ASIC physical design engineer sought to develop and sign off on cutting-edge silicon for SpaceX Starlink. Responsibilities include partition synthesis and physical implementation (synthesis, floorplanning, power/ground grid generation, place-and-route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency, signoff checks), developing/improving physical design methodologies and automation scripts, collaborating with ASIC design to drive timing/power/area targets, resolving design/timing/congestion issues, and performing signoff closures in STA and related flows. Required experience with RTL2GDSII physical design and signoff, EDA tools, deep sub-micron FinFET/CMOS physics, standard cell libraries, DFT/MBIST/LBIST, and scripting (Python, TCL, Bash, etc.). Additional requirements include ability to work extended hours/weekends. Compensation range $160,000–$220,000 per year; comprehensive benefits; ITAR compliance required.
Required Qualifications
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
Desired Qualifications
- Bachelor’s degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
Additional Requirements
- ITAR REQUIREMENTS: U.S. citizen or national, U.S. lawful permanent resident, refugee, asylee, or eligible to obtain required authorizations from the U.S. Department of State.
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