Sr. Principal Engineer, SoC Architect
$250,000–$304,000 year
On-site · San Jose, California, United States
Job Summary
Senior Principal Engineer – SoC Architect responsible for defining end-to-end SoC architecture across compute, memory, interconnect, and peripheral subsystems; drive architectural tradeoffs involving performance, power, area, latency, and scalability; develop architectural specifications, subsystem partitioning, and top-level integration strategies; lead high-speed I/O architecture including PCIe Gen5/Gen6, CXL/UCIe, SerDes; define bandwidth, latency, coherency, buffering, QoS, and interoperability requirements; drive system-level performance modeling and interface optimization; mentor senior engineers and lead architectural reviews, design evaluations, and architecture signoff; collaborate across hardware, firmware, software, RTL, verification, validation, and product teams; engage with external IP vendors as needed; requires 15+ years in SoC architecture and semiconductor product development; strong leadership and communication skills; preferred familiarity with heterogeneous compute, chiplet architectures, advanced packaging, silicon bring-up, and post-silicon validation; salary range $250,000 - $304,000; on-site role in San Jose, CA.
Required Qualifications
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field
- 15+ years of experience in SoC/system architecture and semiconductor product development
- Proven expertise in large-scale SoC architecture definition and subsystem integration
- Strong understanding of High-speed I/O architectures and protocols, On-chip interconnects and coherency fabrics, Memory subsystem architecture, Performance modeling and analysis and Power/performance optimization techniques
- Experience with architecture modeling tools, simulation environments, and performance analysis methodologies
- Strong technical communication and leadership skills
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