Sr. Principal Design Engineer CMOS
$142,200–$213,400 year
On-siteManhattan Beach, California, United States
Job Summary
Lead the design, simulation, and verification of RF and mixed-signal CMOS blocks for space payload applications, defining architectures and performance budgets with systems, digital, and packaging teams. Drive pre- and post-layout analyses to close targets on performance, power, and area, while providing technical direction to layout and junior engineers for radiation-tolerant practices. Plan design reviews, identify risks, and lead silicon bring-up, lab characterization, and debug efforts to correlate simulations with production test strategies. This contingent role requires a Bachelor's, Master's, or PhD in Electrical Engineering with 9, 7, or 4+ years of relevant CMOS design experience, respectively, and proficiency in SPICE-based simulation and Cadence environments. Basic qualifications include demonstrated leadership in transistor-level design and a deep understanding of analog/RF principles. Preferred qualifications encompass experience with radiation-tolerant ICs, RF front ends, and lab validation using measurement equipment.
Required Qualifications
- Bachelor's degree in Electrical Engineering (or related field)
- 9+ years of relevant CMOS design experience
- Master's degree with 7+ years of relevant CMOS design experience
- PhD with 4+ years of relevant CMOS design experience
- Demonstrated leadership in transistor-level CMOS RF and/or mixed-signal IC design through multiple full design cycles
- Deep understanding of analog/RF design principles, including stability, noise, linearity, and layout‐dependent effects
- Proficiency with SPICE-based simulation, Cadence (or similar) design environments, and advanced verification techniques
- Proven experience guiding layout, closing DRC/LVS, and managing block- and top-level integration
- Strong technical communication and experience presenting to cross-functional and leadership audiences
- Active security clearance or ability to obtain a U.S. Government security clearance
- U.S. Citizenship
Desired Qualifications
- IC design experience for space, radiation-tolerant, or other harsh environments (rad-hard design techniques, TID/SEE considerations)
- Experience with RF front ends, data converters, synthesizers/PLLs, or mixed-signal readout ASICs for space payloads
- Hands-on leadership in lab validation and silicon debug using RF and mixed-signal measurement equipment
- Experience mentoring junior engineers and influencing technical direction at the program or product level
- Experience with heterogeneous integration approaches
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