Sr Principal Design Engineer
On-site · Bengaluru, Karnataka, India
Job Summary
Senior principal role focused on high-speed analog/mixed-signal CMOS design for D2D/SERDES products. Lead the design of analog/mixed-signal blocks from concept to verification, collaborating with layout engineers and global teams. Key responsibilities include designing SERDES architectures and blocks (Driver, Receiver, Serializer/Deserializer, Phase Interpolator, PLL, clock distribution, bias networks, voltage regulators), ensuring conformance to customer specifications, and leveraging CAD tools (Cadence) for simulation, layout, and verification. Requires 8+ years of CMOS design experience, proficiency in SERDES/high-speed I/O, understanding jitter and equalization techniques, and experience with CAD tools. Desirable: Cadence expertise and silicon-qualification/test experience; work across US/Canada/India time zones.
Required Qualifications
- BEng, MEng, PhD or equivalent
- minimum 8 years CMOS design experience
- experience in CMOS SERDES or high-speed I/O design
- understanding of jitter and signal equalization techniques
- experience with SERDES circuit blocks (Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, Voltage Regulators)
- CAD tools for circuit simulation, layout, and verification; Cadence preferred
- lab test/silicon evaluation experience advantageous
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