Sr Principal Applications/Validation Engineering
HybridSan Jose, California, United States
Job Summary
Analyze and debug complex technical issues involving server memory, manage customer issues to a satisfactory conclusion, and support technical qualification of new chip designs to secure design wins. Assist with validation and debug of new memory interface chips for DDR5 servers, collect and analyze signal integrity data at the system level, and conduct failure analysis to prepare 8D reports. Gather customer technical feedback, communicate with Marketing and Engineering teams, and present updates via quality presentations. Prepare technical documentation including datasheets, user guides, and application notes. Requires 12+ years of experience, hybrid schedule with three days onsite, and ability to travel internationally.
Required Qualifications
- Familiar with DDR4/DDR5 DIMM memory operation in Intel, AMD, and/or OEM servers
- Good understanding of signal integrity issues at clock rates of 3 GHz and above
- Experience with power management and I2C/I3C serial interfaces
- Extensive experience with probing, using high speed oscilloscopes and other lab equipment
- History of using fundamental root cause techniques (fishbone, design of experiments, etc.) to solve complex problems
- Ability to travel to customer sites as needed, including international travel
- Excellent verbal and written communications skills in English and Korean
- BS degree or higher in Electrical Engineering or related field
- 12+ years of experience in hardware design, validation, and/or applications engineering
Desired Qualifications
- Good understanding of ATE tester operation
- Past experience reading and modifying MRC BIOS code and utilizing server platform debug tools (either Intel or AMD)
- Ability to use scripting languages such as Perl, Tcl or Python to analyze data log text files and automate system and bench testing
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