Sr. Logic Design Engineer
$141,910–$200,340 year
HybridPhoenix, Arizona, United States or Santa Clara, California, United States
Job Summary
Develop logic design, RTL coding, and simulation for IP blocks while participating in architecture and microarchitecture feature definition. Perform quality checks across RTL to timing/power convergence and apply strategies to optimize logic for power, performance, area, and timing goals. Review verification plans and resolve failing RTL tests to ensure design correctness and physical implementation integrity. This role supports Intel's flagship datacenter/server designs within the UCIE PHY IP team, requiring rapid ramp-up on complex IPs in a dynamic environment.
Required Qualifications
- Bachelor's degree in Electrical or Computer Engineering or a related field
- 4+ years' experience
- Master's degree in Electrical or Computer Engineering or a related field
- 2+ years' experience
- PhD in Electrical or Computer Engineering or a related field
- 1+ years' experience
- RTL/Logic design using System Verilog Language
- Design of Data path
- Power-management flow
- Arbitration logic
- Clock Domain Crossing
- State Machines
- UPF
- Front End design tools for Lint, Synthesis
- hardware simulation tools and methodologies (VCS/Verdi)
- IP environment and configuration management tools
- Shift 1 (United States of America)
- US, California, Santa Clara
- US, Arizona, Phoenix
- US, Oregon, Hillsboro
- hybrid work model
Desired Qualifications
- UCIE PHY Design
- Mixed-Signal Environment
- Cross Domain Crossing
- Voltage Domain Crossings
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