Sr. Layout Engineer
On-site · Tokyo, Tokyo, Japan
Job Summary
Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits. Will review and coordinate work content performed by offshore layout designers. Train junior layout engineers and offshore layout contractors. Contribute to developing standard layout methodologies across sites. Contribute to build process and procedures to achieve high layout quality. Requires remote interfacing with local and global design and layout teams in multiple design centers across different time zones. Perform floor-planning, power line planning, shielding, device-matching layout, verify layouts (DRC/LVS/ERC) and support chip-level routing, integration, and tape-out.
Required Qualifications
- BA/BS Degree in Layout Design or related field or equivalent experience
- 10 years’ experience with layout design for analog and full-custom digital blocks
- Experience with TSMC 180nm, 65nm, 22nm process technologies
- Proficient in using Cadence Virtuoso design environment
- Solid knowledge of debugging DRC/LVS/ERC with Cadence PVS or Mentor Calibre
- Conceptual understanding of layout topics such as parasitic, matching, crosstalk, transistor layout dependent effects, latch-up, IR drop, electro migration (EM), and deep N-well and NTN isolation
- Strong capability of solving device matching, electro-migration, signal integrity and power distribution problems while meeting area constraints
- Experience in chip-level floor planning and analog block integration
- Experience chip level integration, verifications, and tape-out
- Ability to use productivity-enhancing tools and design scripts to automate tasks
- Must be able to lift, push, and pull up to 5 lbs
- Attention to detail, organized, accurate and able to produce efficient layout techniques
- Strong communication skills and teamwork in fast-paced environments
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