SR Layout Engineer, DEG
On-site · Boise, Idaho, United States
Job Summary
SR Layout Engineer for DRAM/memory technology responsible for designing and developing IP layouts used in DRAM chips, performing layout verification (DRC/LVS/EM), and delivering block-level layouts on time. Leads sub-block layouts, guides team members, contributes to project management, and communicates with global engineering teams (US, India, Japan) to ensure layout project success. Requires hands-on analog and mixed-signal layout experience with Cadence Virtuoso, knowledge of physical verification and reliability checks, and ability to produce high-performance layouts while considering matching, electromigration, latch-up, crosstalk, IR-drop and parasitics. Preferred background in DRAM/memory circuits and parasitic extraction/post-layout optimization; strong collaboration skills across a global engineering community.
Required Qualifications
- Experience performing physical layout using Cadence Virtuoso or similar tools
- Familiarity with DRC, LVS, physical verification, and reliability checks
- Strong understanding of Circuit Design principles and ability to create high-performance layouts optimized for area
- Hands-on experience with critical analog layout of blocks (e.g., Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Reference Generators, Charge Pump, Current Mirrors, Differential Amplifier)
- Understanding of Analog Layout fundamentals (matching, electromigration, latch-up, coupling, crosstalk, IR-drop, active and passive parasitics)
- Preferred: DRAM/memory circuits background and large-scale hierarchical designs
- Background in parasitic extraction flows and post-layout optimization
- Experience with partial custom layout (devices, small analog blocks)
- Strong communication skills for global collaboration
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