Sr. Engineer, Layout Design
On-site · Bengaluru, Karnataka, India
Job Summary
Sr. Layout Design Engineer will lead top-level chip-planning and perform block-level custom layouts for CMOS and BiCMOS circuits, review and coordinate work by offshore layout designers, train junior layout engineers, and contribute to standard layout methodologies across sites. Responsibilities include leading top-level chip-planning, performing functional-block-level to block-level and standard cell layouts, schematic-driven layout and design constraints, die-area efficient layouts, floor-planning, power line planning, shielding, device-matching layouts, layout verification (DRC/LVS/ERC), chip-level routing and tape-out, and collaboration with global design teams. Requires remote interfacing across time zones and proficiency with Cadence Virtuoso, PVS, or Mentor Calibre, plus experience with TSMC process technologies and layout optimization concepts. Desirable: automation through design scripts and strong communication within fast-paced teams.
Required Qualifications
- BA/BS Degree in Layout Design or related field or equivalent experience
- 10 years’ experience with layout design for analog and full-custom digital blocks
- Experience in TSMC 180nm, 65nm, 22nm process technologies
- Proficient in Cadence Virtuoso design environment
- Strong debugging of DRC/LVS/ERC with Cadence PVS or Mentor Calibre
- Understanding of parasitic, matching, crosstalk, latch-up, IR drop, electro migration, deep N-well and NTN isolation
- Experience in chip-level floor planning and analog block integration
- Ability to automate tasks with scripting
- Must be able to lift up to 5 lbs
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