Sr. Engineer II – Verification
On-site · Bengaluru, Karnataka, India
Job Summary
Senior Verification Engineer to lead verification in Data Center Storage products. Define verification plans and build testbenches for device, subsystem, and IP-level designs using SystemVerilog/UVM. Interpret specifications to drive verification strategy and use coverage-driven verification, ABV, and formal techniques. Execute simulations with Cadence Xcelium and debug with Cadence Verisium Manager. Develop test cases, checkers, and functional coverage models; drive coverage closure; collaborate with firmware, emulation, and silicon validation; support pre- and post-silicon bring-up and debugging; document hardware workarounds. Mentor junior engineers and contribute to process improvements. Travel 0–25%. Desirable: hands-on experience with PCIe, CXL, NVMe, DDR, SAS, SATA; experience with formal verification tools; prior storage/memory controller verification; mentoring or technical leadership.
Required Qualifications
- Bachelor's degree with 8–10 years of silicon verification experience, or Master's degree with 6–8 years of experience
- Proficiency in RTL verification using CDV methodologies
- HDL/HVL languages: SystemVerilog, Verilog, or VHDL
- Industry protocols such as AXI, APB, AHB
- Strong programming in C and/or C++
- Scripting experience (Python, Perl, TCL, Shell, etc.)
- Unix/Linux environment familiarity
- Version control experience (Git, SVN)
- Excellent written and verbal communication
- Ability to work independently and in a fast-paced team
Desired Qualifications
- SystemVerilog
- UVM
- CDV
- ABV
- formal verification
- Cadence Xcelium
- Cadence Verisium Manager
- HDL
- Verilog
- VHDL
- C/C++
- Python
- Scripting
- Unix/Linux
- Git/SVN
- NVMe
- PCIe
- CXL
- SAS
- SATA
- verification plans
- testbenches
- coverage-driven verification
- pre-silicon emulation
- post-silicon validation
- Mentoring
- team collaboration
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