Sr. Engineer, ASIC Physical Design
On-site · Bengaluru, Karnataka, India
Job Summary
Senior ASIC Physical Design Engineer responsible for the physical design and integration of complex SoCs with digital blocks, analog/mixed-signal blocks, and photonics components for a high-speed electro-optical engine. Role emphasizes synthesis, place-and-route, timing closure, and physical verification, and involves coordinating activities across multiple designers, contributing to DFT and automated design methodologies, and advancing CAD flows. Requires strong background in Verilog RTL, ASIC synthesis and signoff tools, timing analysis, clock tree synthesis, DFT, and scripting; preferred experience with Cadence Virtuoso, Python, 3DIC, and SerDes; note about recruiters included.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or related fields
- 2+ years of work experience in ASIC physical design
- History of leading successful block implementations integrating custom IP in leading edge process nodes
- Proficient in Verilog RTL
- Mastery of ASIC synthesis (RTL Compiler, Genus, Design Compiler), place-and-route (Encounter, Innovus, ICC), and physical verification (DRC, LVS)
- Mastery of timing constraints and deep understanding of static timing analysis
- Proficient in clock tree synthesis methodologies and customization
- Proficient in designing DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Proficient in ASIC signoff methodologies, checklists, and requirements
- Proficient in scripting or programming languages
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