SR Engineer, ASIC DFT
On-site · Bengaluru, Karnataka, India or Hyderabad, Telangana, India
Job Summary
Senior DFT engineer responsible for innovative DFT implementation (Scan, MBIST, LBIST & Boundary Scan) at RTL and gate level for SOCs, generating and validating ATPG patterns, and supporting silicon bring-up to ensure robust test patterns. Collaborates with RTL, DV, Physical Implementation, Test, and Product Engineering teams; expects strong hands-on experience in DFT methodologies, multi-functional team communication across geographies, and proficiency with industry tools for verification and test pattern development. Nice-to-have knowledge includes IEEE 1149.6/1500/1838, hierarchical scan with core wrapping, multi-clock domain and low power DFT, and 2.5D/3D IC DFT concepts; must be able to communicate effectively with global teams and manage multiple tasks.
Required Qualifications
- Bachelor’s or Master’s Degree in Electronics Engineering, Microelectronics, Software Engineering or related field
- 5+ years of industry experience in DFT of SOCs
- Experience with Scan Codec insertion, Memory BIST and Repair implementation, Logic BIST, ATPG, BSCAN & JTAG (IEEE1149.1 & IEEE1687)
- SDF annotated gate level verification
- Scan and Memory Diagnosis
- Experience with Siemens, Synopsys and/or Cadence CAD tools
- Verilog, VHDL, C/C++, TCL, Perl and/or Python
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