Sr. ASIC Design Engineer
$168,000–$336,000 year
On-site · San Jose, California, United States
Job Summary
Senior ASIC Design Engineer responsible for logic design across the full ASIC lifecycle—from specifications and microarchitecture through design, integration, synthesis, timing, linting, and CDC; leverage GenAI and agentic tools to drive efficiency and execution; requires 5+ years of experience, a Bachelor's degree in Electrical Engineering or Computer Science, and strong proficiency with SystemVerilog, EDA flows, and bus protocols (PCIe, NVMe, AXI) plus exposure to CPU architectures and memory interfaces; knowledge of AI/LLMs and machine learning is highly desirable; salary range for US roles is $168,000–$336,000 plus benefits and equity.
Required Qualifications
- 5+ years of proven experience
- Bachelors degree in Electrical Engineering or Computer Science related major
- Hands-on experience with GenAI, including development of agentic MCP and skill-based tools
- Proficient in EDA tools and flows, including digital design, simulation, SystemVerilog, static timing analysis, synthesis, timing closure, and top-level integration (clock and IO)
- Knowledge of AI/LLMs and machine learning, PCIe, NVMe, DRAM, NAND interfaces, AXI, CPU architecture, and bus protocols
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