Sr. ASIC Design Engineer
$153,500–$310,500 year
On-siteSunnyvale, California, United States
Job Summary
Develop detailed micro-architecture specifications for high-speed ASIC modules meeting power and area constraints, then implement designs in Verilog or System Verilog. Generate functional coverage and SystemVerilog Assertions to verify corner cases, collaborate with Physical Design teams for floorplan and timing closure, and fix RTL timing to meet frequency targets. Partner with Verification teams to ensure full block validation and mentor new college-grad engineers and interns. Work within HPE Networking Silicon group to build cutting-edge networking chips used in world-class routers and switches, advancing edge-to-cloud connectivity.
Required Qualifications
- Bachelor's degree in Electrical Engineering
- 5+ years of relevant experience
- Strong analytical/problem solving skills
- Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work
- Strong coding skills in Verilog/System Verilog
- Knowledge of synthesis/lint and other state-of-the-art EDA tools
- Excellent written and verbal communications skills
- Knowledge of Perl/Python
- Experience with AI agentic tools
- Onsite work from an HPE office
Desired Qualifications
- Master's degree
- Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus
- Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired
- Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired
- Excellent written and verbal communications skills are good to have
- Knowledge of Perl/Python is a plus
- Experience with AI agentic tools is a plus
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