Soc Subsystem Architect - AI platform Development

Architect AI platform-focused SoC subsystem; lead evaluation of architectural trade-offs under feature, performance, and power constraints; define micro-architecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver fully verified, synthesis- and timing-clean designs; collaborate with verification teams for coverage and validation; develop timing constraints for IP blocks and support physical design for synthesis and timing closure; drive silicon bring-up and post-silicon validation including debug and performance analysis; mentor junior engineers and contribute to design-methodology best practices.