SoC Static Timing Analysis (STA) Engineer, HBM

Drive development of AI-hardware for next-gen LLM workloads and apply generative AI to enable AI-enabled timing closure methods. Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory interfaces, design for test, and configuration logic. Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, engineering change orders, and close collaboration with physical design on placement, clock tree synthesis, and routing. Perform multi-mode, multi-corner analysis including clock domain crossing timing, on-chip variation, and advanced-node methodologies. Lead signal integrity and crosstalk analysis, identify noise-induced timing issues, and partner with physical design teams on mitigation strategies. Build and maintain static timing analysis automation and flows using Python and Tcl for reporting, regression tracking, quality of results dashboards, and sign-off readiness. Conduct post-silicon timing correlation and develop organization-wide static timing analysis methods. Define sign-off standards, timing closure guidelines, readiness reviews, and tape-out sign-off gates. Communicate timing status, risks, and closure plans clearly to design leads and senior management.