SoC/IP Design Verification Engineer
On-siteGuadalajara, Jalisco, Mexico or San José, San José, Costa Rica
Job Summary
Own the verification lifecycle for SoC/IP blocks, including requirements decomposition, UVM testbench architecture, and coverage closure strategies. Develop constrained-random test content, debug failures across simulation and emulation, and drive signoff with stakeholders. Collaborate cross-functionally with design, architecture, and validation teams to ensure feature completeness and testability while improving verification flows and infrastructure. Requires 5+ years of SoC/IP verification experience, UVM expertise, and unrestricted right to work in Mexico. On-site presence required in Guadalajara.
Required Qualifications
- English version of resume
- Bachelor's degree in Electrical Engineering, Computer Engineering or in a related field
- 5+ years of experience in: SoC/IP design verification experience
- UVM/SystemVerilog development expertise (testbenches, agents, scoreboards, virtual sequences, factory/objection/callback mechanisms)
- Test planning experience: translating architectural/RTL specs into measurable, coverage-driven verification plans
- Proven debug skills in simulation/emulation (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa; waveform tools like Verdi/DVE/SimVision)
- Coverage-driven verification: functional coverage modeling, code coverage analysis, coverage closure workflows
- Scripting proficiency (e.g. Python, Shell, Make/CMake) for automation, regressions, and data analysis
- Advance English level
- Must have unrestricted, permanent right to work in Mexico (this role is not eligible for vi-sa or immigration sponsorship)
- On-site presence
- Behavioral Traits: Problem-Solving Mindset: Approaches complex technical challenges with curiosity, creativity, and structured analytical thinking
- Behavioral Traits: Collaboration Skills: Works effectively with cross-functional engineering teams, seeks input from partners, and communicates clearly in both technical and non-technical contexts
- Behavioral Traits: Adaptability and Learning Agility: Quickly learns new tools, technologies, and methodologies; comfortable working in evolving development environments
- Behavioral Traits: Attention to Detail: Delivers high-quality, reliable, and scalable software solutions with a focus on robustness, validation, and secure coding practices
- Behavioral Traits: Results-Oriented: Prioritizes effectively, manages time well, and drives solutions to completion in a fast-paced engineering environment
- Behavioral Traits: Innovation and Continuous Improvement: Looks for opportunities to optimize tools, simplify workflows, and introduce new methodologies that enhance engineering efficiency
Desired Qualifications
- SoC-level verification experience: fabric/interconnect, security
- Experience with standard protocols: AXI/ACE/CHI, PCIe, LP/DDR, USB, MIPI, I3C, SPI/I2C, Ethernet; integrating and customizing VIP
- Assertion-based verification (SVA) and formal (JasperGold/VC Formal/PropCheck) for property checking and bug hunting
- Power-aware verification (UPF/CPF), isolation/retention, multi-voltage domains
- Emulation/FPGA prototyping (Palladium, Zebu, Veloce), transaction-level acceleration, hybrid verification
- Performance/latency/throughput test content and checkers; scoreboard/reference model design for complex data paths
- Exposure to C/C++/SystemC reference models or firmware-aware verification
- Experience leading small teams, mentoring, or driving signoff for a tapeout
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