SoC Compute/Memory Subsystem Architect
$82,720–$153,670 year
Hybrid · Leixlip, Leinster, Ireland
Job Summary
Lead end-to-end SoC compute and memory architecture for IPU/DPU platforms, defining cache coherency, memory subsystems, SMMU/IOMMU, virtualization, and cross-functional integration across compute, network, storage, and accelerators in hyperscale environments. Drive architecture from concept to silicon with a focus on power efficiency, DVFS scaling, and performance-per-watt, collaborating with NSS, SoC fabric, firmware, OS, drivers, validation, and performance modeling. Requires strong architectural vision, systems thinking, decision-making under ambiguity, and leadership with a customer-oriented mindset; hybrid work model in Ireland.
Required Qualifications
- Bachelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study
- 10+ years of experience in SoC / CPU / memory subsystem architecture
- Experience with CPU architecture and cache hierarchies
- Experience with memory subsystems (DDR/HBM, controllers, QoS)
- Experience with coherent/non-coherent interconnect architectures
- Experience with system-level performance and PPA tradeoff analysis
- Ability to drive architecture definition from concept to silicon
- Preferred: ARM and x86 compute and memory subsystem experience, NUMA systems, cache coherency, large-scale platform architectures
- Preferred: IPU/SmartNIC or accelerator-centric SoCs in cloud/hyperscale environments
- Familiarity with PCIe, CXL, and memory semantics for high performance IO
- Track record of multi-generation architectural ownership and mentoring
- Post Graduate degree in Electrical/Computer Engineering or STEM field
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.