SMTS Logic Design
HybridMontréal, Quebec, Canada or Montreal, Wisconsin, United States
Job Summary
Conduct architecture and micro-architecture development for next-generation PCIe Gen6/Gen7 switch products, defining complex hardware subsystems including switch fabric, port controllers, and routing logic. Develop high-quality, synthesizable RTL using SystemVerilog to implement timing-conscious, physically-aware pipelines supporting Gen6 and Gen7 data rates. Lead independent design block development, drive resolution of complex technical issues, and mentor junior engineers while collaborating with verification teams on strategies and debug approaches. Support emulation, FPGA, and silicon debug activities, enforce coding guidelines, and participate in continuous improvement of design methodologies. Work directly with Logic Design leadership in a hybrid environment requiring three days onsite per week.
Required Qualifications
- BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related discipline
- 8+ years of ASIC/SoC logic design experience with proven delivery of complex silicon products from architecture through tape-out
- Expert knowledge of SystemVerilog, RTL design methodologies, and ASIC development flows
- Strong understanding of pipelined architectures, resource arbitration, state machine design, clock-domain crossing (CDC), reset-domain crossing (RDC), and low-power design techniques
- Experience with synthesis and timing closure, including industry-standard EDA tools such as Synopsys Design Compiler/Fusion Compiler, Cadence Genus, SpyGlass, and Questa/Visualizer
- Strong problem-solving, analytical, communication, documentation, mentoring, and technical leadership skills, with the ability to work effectively across architecture, verification, software, and customer-facing teams
- Must be able to spend an average of at least three days per week onsite
Desired Qualifications
- deep knowledge of PCIe Gen5/Gen6/Gen7 protocol architecture and experience designing PCIe switches, root complexes, PCIe endpoints, or high-speed interconnect fabrics
- familiarity with CXL, PTM, ATS/PASID/PRI, SR-IOV, and PCIe power management features
- experience with emulation platforms such as HAPS, Palladium, or Veloce, and experience with performance modeling or architectural simulation in Python or C++
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