Signal Integrity Engineer - Serdes, Satellites (Starlink)
$105,000–$145,000 year
On-siteRedmond, Washington, United States
Job Summary
Specify, design, simulate, verify, qualify, and troubleshoot signal integrity aspects of advanced satellite hardware, including wireline and electro-optical communication systems with SERDES, DSPs, and high-speed memory interfaces. Derive top-level specifications for PCB materials, design transition structures from die bump to die bump, and root cause issues found in manufacturing, testing, or integration. Define design processes, simulation workflows, test methodologies, and signoff criteria while collaborating with RF, antenna, ASIC, and packaging engineers to architect novel channel and power delivery strategies. Spread knowledge and techniques across the Starlink program to optimize package, PCB, and mixed-signal circuits for best-in-class products.
Required Qualifications
- Bachelor's degree in electrical engineering, computer engineering, or physics
- 1+ years of industry experience designing circuits, electronic products, or hardware
- 1+ years of experience using one of the 3D EM simulation tools and high-speed digital channel simulators (CST, HFSS, ADS etc.)
- 1+ years of research or industry experience with high-speed digital design
- Ability to work extended hours or weekends as needed for mission critical deadlines
- Some travel may occasionally be required
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State
Desired Qualifications
- Master's degree or PhD in electrical engineering, computer engineering with emphasis in electromagnetic theory, transmission line theory, or wireline transceivers
- 3+ years of electronic product experience designing hardware from concept through production
- 3+ years of experience architecting, implementing, and debugging cutting edge DSP based SERDES products (i.e. 56Gbps, 112Gbps, 224Gbps)
- 3+ years of experience specifying, analyzing, debugging, and working with high speed, high bandwidth memory interfaces
- Thorough understanding of wireline transceiver concepts, architectures, and circuits
- Strong understanding of computers and programming languages (Python, C/C++)
- Demonstrated ability to work in a highly cross-functional role
- Experience with low loss laminates, high volume PCB manufacturing, and high-speed connectors
- Experience debugging and resolving EMI/EMC de-sense problems
- Passion for working in dynamic cross-functional role to optimize package, PCB, ASIC, mixed signal circuit to deliver best in class products
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