Serdes Digital Design Architect
On-siteGeorge Town, Penang, Malaysia
Job Summary
Define and document the digital micro-architecture for PMA/PMD/PCS blocks, including DSP datapaths and control processors. Write high-quality Verilog RTL, verify it using directed and UVM methods, and debug corner cases across multiple asynchronous clock domains. Collaborate daily with analog designers to model mixed-signal effects, craft timing constraints, and run STA to close timing in cutting-edge FinFET nodes. Drive lint, CDC, and RDC clean-up while exploring FPGA platforms to validate algorithms and bring-up firmware pre-silicon. Contribute to embedded microcontroller firmware for calibration, adaptation, and link-training routines. This veteran architect will own the digital subsystems of the next-generation 112 Gb/s-and-beyond Ethernet SerDes, translating high-level requirements into clean RTL that meets strict power, performance, and area targets.
Required Qualifications
- Master's degree or higher in Electrical Engineering
- 10+ years of hands-on experience architecting and implementing high-speed (>32 Gb/s) SerDes or similar high-performance mixed-signal IPs
- Deep expertise in Verilog/SystemVerilog, synthesis, and STA
- familiarity with physical design flows (floor-planning, CTS, routing, IR-drop, EM)
- Proven ability to balance PPA trade-offs and to communicate them clearly to both analog and digital peers
- Solid grasp of DSP concepts and algorithms (FFE, DFE, CTLE, FEC)
- Working knowledge of the Ethernet protocol stack (IEEE 802.3bs/cd/cg) and PMA/PMD/PCS layer requirements
- Comfortable with multi-clock-domain design, CDC strategies, and industry-standard verification tools
- Self-starter who can triage issues across RTL, gate-level netlists, and lab silicon
Desired Qualifications
- FPGA/emulation bring-up experience
- Embedded C/Firmware development for RISC-V or proprietary microcontrollers
- Exposure to advanced process nodes (7 nm, 5 nm, 3 nm)
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