Senior Yield Enhancement Engineer
$175,000–$250,000 year
On-site · Sunnyvale, California, United States
Job Summary
Senior Yield Enhancement Engineer with 7+ years in semiconductor test/FA/yield enhancement. Analyze ATE data logs, Shmoo plots, and defect patterns; develop FA tools using optical, photo emission, and laser-based defect localization; execute FIB edits for root-cause validation; collaborate with DFT, silicon architects, and software teams to enhance testability and yield; refine test programs around di/dt, voltage-frequency characterization, and thermal constraints; strong Python/UNIX experience; Sunnyvale, CA-based with up to 20% travel; base salary $175k-$250k with potential bonus/equity.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering / Computer Engineering, or related field
- 7+ years of hands-on experience in semiconductor test engineering/ FA/ Yield Enhancement
- Hands-on experience with lab debug tools: Oscilloscopes, wafer probe stations, probe cards, Keyence/Optical inspection systems
- Failure analysis expertise with optical probing tools, physical inspection workflows, and correlation of electrical failures to physical defects
- Strong understanding of Digital CMOS layouts, power grids, routing structures and SRAM arrays
- ATE test program debugging and yield improvement experience
- Proficiency in programming languages: Python, C/C++, Perl
- Experience communicating with OSATs and fabs to drive production testing in HVM environment
- Experience with shmoo plots, parametric data, and ATE data analytics
- DFT strategies including hierarchical scan chains, distributed BIST, SRAM test methodologies
- Knowledge of git repositories, GitHub, and CI/CD workflows
- Preferred: OBIRCH/IREM/LADA optical techniques, machine learning for yield optimization
- Location: North America based; Sunnyvale with up to 20% travel
- Base salary range: $175,000 to $250,000 annually
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