Senior Verification Engineer, Switch SoC
HybridBengaluru, Karnataka, India
Job Summary
Define project milestones using internal roadmaps within the agile framework and develop system-level methodologies, tools, and IPs to build SOCs efficiently. Work on SOC Assembly, driving cross-functional teams toward milestone execution and integrating all project pieces to deliver models for verification at cluster, sub-system, SOC, and emulation levels. Maintain a strong grasp of Perl, Python, or industry-standard scripting languages while collaborating with software teams to define HW/SW interfaces. This role supports the Networking Chip Design team in India, a new unit crafting next-generation Switch Silicon chips for high-speed communication devices.
Required Qualifications
- BS (or equivalent experience) / MS
- 4+ years of practical semiconductor design and architecture experience building complex SoC's
- firsthand experience & solid understanding of all phases of SOC development in multiple ASIC projects including ASIC architecture, Micro-Architecture, RTL design, verification, timing closure & Physical design
- Exposure to design and verification tools (Verilog/SV or equivalent, Cadence or equivalent simulation tools, debug tools like Indago, GDB etc.)
- Experience working with software teams to tightly define the HW/SW interface including control/status registers, interrupt and error handling
- Hands on experience in successful tape outs of multiple complex, high-volume SoCs in advanced process nodes
- Exposure to various Chip Design Functions to be able to collaborate and solve complex cross functional problems
- Excellent verbal and written communication skills to interact with cross functional teams to build consensus
- Good teamwork spirit and collaboration skills with team members
Desired Qualifications
- C/C++ programming or python or any other industry-standard scripting language experience
- Experience in synthesis, physical design and DFT
- RTL Build and Design Automation
- Chip lead type of technical leadership experience on delivering complex SOCs for enterprise and/or HPC applications
- Experience in RTL coding and debug, as well as performance/power/area analysis and trade-offs
- Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area
- Strong coding skills in Perl, Python, or other industry-standard scripting languages
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