Senior Verification Engineer
On-siteRiga, Riga, Latvia
Job Summary
Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs. Create directed-random test scenarios, assertions, and functional coverage while executing simulation-based verification using industry-standard simulators. Drive debug and root-cause analysis of functional issues, integrate VIPs and scoreboards, and support regression runs and release signoff. Review RTL and test plans to ensure quality, mentor junior engineers, and contribute to verification best practices. Assist with FPGA bring-up and validation on evaluation boards. This role requires 6-9 years of functional verification experience and strong analytical skills within a cross-functional team.
Required Qualifications
- 6-9 years of hands-on experience in functional verification
- Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field
- Strong hands-on expertise in SystemVerilog and UVM
- Experience with hardware/software co-verification
- Knowledge of high-speed interfaces (AXI, AXI‐Stream, DDR, SPI)
- Strong analytical and debugging skills
- Ability to work effectively in cross-functional teams
- Excellent written and verbal communication skills
- Self-driven with the ability to own verification tasks end-to-end
- High attention to detail and commitment to quality
- Working knowledge of Verilog and VHDL
- Ability to use a computer for extended periods
- Ability to work in a standard office environment
- Occasional lab work for FPGA bring-up and debug
Desired Qualifications
- Familiarity with cadence tools like Xcelium
- Familiarity with Xilinx Vivado
- Experience with hardware/software co-verification
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