Senior Technical Staff Engineer - Design (IO)
$91,000–$232,000 year
On-site · San Jose, California, United States or Roseville, California, United States
San Jose, California, United States or Roseville, California, United StatesOn-siteFull Time$91,000–$232,000 yearSenior LevelMasters DegreeEnterprise
Type
Full Time
Level
Senior Level
Education
Masters Degree
Company size
Enterprise
Job Summary
Senior Technical Staff Engineer in IO Design leading pad ring planning, IO cell placement, and bump pattern development for advanced SoC designs; collaboration with cross-functional teams on DEF/Verilog netlists, JTAG/TAP controller integration, and post-silicon verification; requires Verilog/SystemVerilog proficiency, IO interfaces (SerDes, DDR, PCIe, CXL), and DFT familiarity; travel up to 25%.
Required Qualifications
- B.S or M.S degree in electrical engineering
- 12+ years related experience
- Hands-on experience with pad ring planning, IO cell placement, and bump map/pattern definition for advanced SoC designs
- Knowledge of IO library cells, IO standards, and PHY-level IO interfaces (SerDes, DDR, PCIe, CXL)
- Experience with IO planning and implementation EDA tools (e.g., Orbit IO, ISP or equivalent)
- Experience generating and validating IO connectivity deliverables (pad ring DEF, IO netlist, bump assignment)
- Experience with Verilog/System Verilog is required
- Basic to intermediate knowledge of JTAG/Boundary Scan (IEEE 1149.1) architecture and TAP controller operation
- Travel 0-25%
- Excellent analytical, communication (written and verbal), and documentation skills
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