Senior Sustaining Hardware Engineer
$130,000–$225,000 year
On-site · Santa Clara, California, United States
Job Summary
Design, debug, and sustain high-speed networking hardware for data center and hyperscaler environments. Responsibilities include root-cause analysis and fixes to the design team and customers, reading logs, identifying bugs, implementing fixes with minimal field impact, developing new tests, and presenting root-cause analyses to executives and customers. Proficiency in FPGA/Verilog, PCIe/DDR interfaces, signal and power integrity, lab measurements, and collaboration with firmware, schematic, BOM, and fab teams is required.
Required Qualifications
- BSEE or MSEE
- 5+ years of relevant hardware engineering experience
- Experience debugging Networking Hardware
- Experience with design of 20+ layer count boards featuring 50G+ signals
- Experience debugging and validating multi-phase DC/DC’s for high current, high transient loads
- Experience with design and debug of high speed interfaces (DDR, PCIe) as well as low speed signals (I2C, SPI)
- Familiarity with signal integrity and power integrity concepts and tools (impedance, PDN’s, Bode plots, PCIe analyzers, TDRs, VNAs)
- FPGA design using Verilog
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