Senior/Staff Front-End Engineer (RTL Design)
On-siteGeorge Town, Penang, Malaysia
George Town, Penang, MalaysiaOn-siteFull TimeSenior LevelMasters DegreeMedium
Full TimeSenior LevelMasters DegreeMedium
Job Summary
Conduct microarchitectural design and implementation using Verilog HDL based on architectural specifications for ASIC chips. Lead design reviews, ensure delivery quality control, and manage soft and hard IP identification, selection, and integration. Collaborate with verification and emulation teams to develop test plans and debug issues, while working with implementation teams to close designs on synthesis, timing, and power constraints. Participate in architectural discussions and drive the RTL design flow from tape-out through deployment.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields
- 3+ to 5+ years of meaningful experiences related to RTL design on ASIC with tape-out experiences
- Familiar with industrial standard RTL design and delivery flow
- Strong understanding of computer architecture and VLSI design
- Experience in GPGPU/NPU/CPU module design, including but not limited to work scheduler, memory subsystem, vector processor core, tensor processor core
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