Senior/Staff Front-End Engineer (IP Integration)
On-siteSingapore, Singapore
Singapore, SingaporeOn-siteFull TimeSenior LevelMedium
Full TimeSenior LevelMedium
Job Summary
Implement Verilog RTL for PCIe IP integration, configuration, and performance evaluation. Support verification closure by ensuring 100% functional coverage and contribute to design verification across pre-silicon and post-silicon stages. Assist in debugging issues and support software development while collaborating with verification and software teams to deliver robust IP solutions. This role focuses on developing and implementing RTL for PCIe-related IP blocks within Bitdeer's global Bitcoin mining and AI cloud infrastructure.
Required Qualifications
- Master's degree (preferred) or Bachelor's degree in Electrical Engineering, or Computer Engineering
- 5 years or more in a semiconductor or high technology R&D experience
- Verilog RTL development experience with industry-standard tools in an SoC/IP environment
- PCIe IP integration experience
- Strong understanding of PCIe architecture and logic design
- Strong problem-solving and debugging skills
- Comfort with scripting languages (Perl, Shell, TCL) to automate design tasks
Desired Qualifications
- Master's degree (preferred)
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