Senior/Staff Front-End Design Engineer (RTL Design - RiscV)
On-siteSingapore, Singapore
Job Summary
Integrate commercial RISC-V core soft IP with external accelerators using custom extension instruction interfaces, tailoring microarchitecture to meet strict performance, power, and area requirements. Modify targeted Verilog/SystemVerilog RTL design for the processor front-end and control path to support customized architectural features. Drive Front-End ASIC implementation steps including synthesis, static timing analysis closure, power reduction, and floorplanning while collaborating with performance, middle-end, and back-end engineers. Contribute to design verification efforts and assist in debugging complex logic issues across pre-silicon and post-silicon stages.
Required Qualifications
- Master's degree (preferred) or Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science, with a strict focus on computer architecture
- Familiarity with the RISC-V ISA, particularly custom extensions, extension instruction interfaces, privilege modes, and Control and Status Registers (CSRs)
- Strong understanding of CPU architecture and logic design, with prominent, hands-on experience in CPU core integration, technical specification drafting, and IP feature tailoring/pruning
- Extensive Verilog RTL development experience using industry-standard tools
- Proven working experience collaborating with performance modeling/engineering teams, middle-end engineers (synthesis/DFT), and back-end (P&R) engineers
Desired Qualifications
- Synthesis flows, linting, CDC/RDC analysis, and static timing analysis (STA)
- SoC-level power-saving techniques, clocking architectures, reset/power-up sequences, and low-power microarchitecture development
- DFT, DFX, MBIST techniques
- Comfort with writing in scripting languages (Python, Perl, Shell, TCL) to automate design
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