Senior Staff Engineer, Design For Test
On-siteHyderabad, Telangana, India
Job Summary
Lead DFT implementation for assigned SoC partitions and IP blocks across Custom and XPU programs, managing scan insertion, MBIST, IJTAG, and ATPG pattern generation with Tessent or TestMax. Execute DFT flows from RTL through gate-level, including Spyglass DRC, LEC equivalence checking, STA for DFT test modes, and TDV optimization. Develop and maintain DFT scripts, automation, and methodology improvements within the M1DPx flow infrastructure. Support post-silicon bring-up by debugging scan chains, ATPG pattern failures, and IJTAG network commissioning on ATE and bench. Collaborate with Physical Design teams on scan chain assignment and DFT physical integration while mentoring junior engineers. Drive DFT deliverables on schedule, ensuring coverage closure, MPR sign-off, and test program handoff to product engineering.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
- 8+ years of DFT experience
- Solid hands-on DFT execution experience: scan insertion, MBIST, JTAG/IJTAG, ATPG (SAF/TDF), EDT compression, and DFT validation (Spyglass DRC, simulation)
- Proficiency with Siemens Tessent and/or Synopsys TestMax for DFT insertion and ATPG
- Experience executing DFT in an RTL-based insertion flow (e.g., Tessent RTL flow) and/or gate-level DFT flow
- Working knowledge of LEC, STA for test modes, scan chain optimization, and TDV management
- Good communication skills
- Ability to work effectively in a multi-site, geographically distributed team
- Track record of delivering DFT on schedule for complex SoC designs at 7nm or below
Desired Qualifications
- Experience with post-silicon bring-up and ATE debug
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