Senior Staff Engineer, Compiler
On-siteKodaira, Tokyo, Japan
Job Summary
Lead AI compiler architecture across model ingestion, graph optimization, lowering, code generation, and runtime integration for Renesas next-generation automotive System-on-Chip platforms. Design and implement graph-level optimizations including operator fusion, quantization-aware rewrites, and memory-aware scheduling to drive performance for target NPUs. Partner with SoC and AI accelerator architects to influence hardware features through compiler insights while owning performance KPIs for real automotive AI workloads using simulators and profilers. Ensure compiler outputs meet automotive requirements for real-time behavior and determinism. Mentor senior engineers and set technical direction without people-management responsibilities.
Required Qualifications
- MS/PhD (or equivalent experience) in Computer Science, EE, or related field
- Deep experience building AI compilers, accelerator backends, or graph optimization frameworks
- Strong expertise in graph optimization and performance optimization for NPUs or custom accelerators
- Experience with MLIR, LLVM, TVM‐like systems, or proprietary compiler IRs
- Excellent C/C++ and Python skills
- Solid understanding of AI inference workloads (CNNs, transformers, perception or generative models)
- Strong communication skills
- Agile development experience in Scrum team (Product Owner or Scrum Master)
Desired Qualifications
- Experience with automotive or safety‐critical systems
- Background in heterogeneous SoCs (CPU/GPU/DSP/NPU)
- Performance modeling or hardware–software co‐design experience
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.