Senior Staff Digital Design Engineer

Senior Staff Digital Design Engineer responsible for RTL design using Verilog/SystemVerilog for digital IP blocks and subsystems, translating architectural specifications into synthesizable RTL, performing linting, CDC and low-power checks, and analyzing timing, area, and power tradeoffs during design implementation. Must support synthesis and collaborate with physical design teams on timing closure, and debug functional issues across simulation, emulation, FPGA prototyping or silicon bring-up. Qualifications include a Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, Computer Science, or related field; demonstrated ownership of at least one major sub-circuit block from architecture definition to fine tuning; mentoring of less experienced teammates; knowledge of communication and DSP algorithms preferred; verification experience with UVM is a big plus. Expected Base Pay Range (USD) 135,900 - 201,130 per annum. Our comprehensive benefits cover financial well-being, family support, mental and physical health, and recognition, with programs like an employee stock purchase plan and various supportive resources. All qualified applicants will receive consideration without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. This position may require export control compliance and related screening.