Senior Staff Design Verification Engineer – Memory Sub-System (LPDDR/DDR/HBM )
$134,390–$201,300 year
On-site · Santa Clara, California, United States
Job Summary
Develop and execute verification plans for high-speed memory interfaces (DDR4/DDR5, LPDDR4/LPDDR5, HBM2/HBM3); build and enhance UVM/SystemVerilog-based verification environments; develop test benches, sequences, and checkers for functional and performance validation; perform protocol-level verification for memory controllers and PHY interfaces; analyze and debug simulation failures, identify root causes, and drive resolution; work closely with design, architecture, and firmware teams to ensure coverage closure and testability; contribute to coverage-driven verification (CDV) including functional, code, and assertion coverage; support emulation/FPGA validation and post-silicon bring-up (nice to have); review design specifications and provide feedback for testability and robustness
Required Qualifications
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or related field
- 5-10 years of ASIC/SoC verification experience
- Strong knowledge of DDR, LPDDR, or HBM protocols and architecture
- Expertise in SystemVerilog and UVM methodology
- Experience debugging complex verification issues
- Familiarity with industry-standard tools (simulation, waveform debugging, and coverage tools)
- Solid understanding of digital design fundamentals
- Preferred: knowledge of JEDEC standards for DDR/LPDDR/HBM
- Preferred: exposure to emulation platforms (e.g., Palladium, Veloce) and scripting (Python/Perl/Shell)
- Experience with low-power verification (UPF)
- Ability to collaborate across design, architecture, and firmware teams
Desired Qualifications
- Strong knowledge of DDR, LPDDR, or HBM protocols and architecture
- Experience with SystemVerilog and UVM
- Debugging complex verification issues
- Scripting skills (Python/Perl/Shell)
- Experience with emulation platforms (e.g., Palladium, Veloce) or post-silicon bring-up
- Exposure to coverage-driven verification (CDV) and testbench development
- Knowledge of JEDEC standards for DDR/LPDDR/HBM (preferred)
- Experience with memory controller/phy verification
- ASIC/SoC verification background
- RTL/verification collaboration across design, architecture, and firmware teams
Apply with one swipe on Sorce. We auto-fill applications and apply on your behalf — no cover letters, no 40-minute forms.
Hiring someone like this?
Get your role in front of qualified candidates on Sorce.