Senior Staff Design Verification Engineer – Coherent Interconnect
On-siteBoston, Massachusetts, United States or Austin, Texas, United States
Job Summary
Own verification planning and execution for a scalable cache-coherent interconnect subsystem, from block-level verification through subsystem integration and signoff. Define verification strategy, test plans, environments, and closure criteria for coherent traffic, ordering rules, backpressure, flow control, buffering behavior, QoS, and error handling. Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models to validate complex interconnect and protocol behavior. Drive verification of subsystem behavior across interface boundaries, protocol adaptation layers, and bridge paths, including CHI, ACE, CXL, and related coherent interconnect flows. Create high-value directed and constrained-random scenarios that expose corner cases in coherency, concurrency, credits, arbitration, QoS, and bandwidth-sensitive behavior. Partner closely with architecture, RTL, formal, and software teams to review specifications, close ambiguities early, and improve overall verification quality. Debug failures efficiently, isolate root cause, and drive fixes across RTL, assertions, testbench infrastructure, and test content. Contribute to methodology and infrastructure improvements that benefit the broader horizontal interconnect verification effort, not just the block directly assigned to you. Mentor engineers and help raise verification quality across the team.
Required Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field
- 8+ years of experience in ASIC or SoC design verification
- Strong hands-on experience with SystemVerilog
- Strong understanding of cache-coherent systems
- Strong understanding of on-chip interconnects
- Strong understanding of memory subsystem behavior
- Strong understanding of verification of ordering and flow-control semantics
- Strong protocol knowledge in CHI, ACE, CXL, AXI, or similar coherent and high-performance interconnect standards
- Experience creating test plans
- Experience creating assertions
- Experience creating coverage models
- Experience creating debug workflows
- Strong scripting and automation skills in Python or similar languages
- Strong communication skills
- Ability to work effectively across architecture, RTL, and verification teams
- Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs
- Experience with protocol-conversion or bridge-heavy subsystems
- Experience with formal verification
- Experience with performance-oriented verification
- Experience with emulation / FPGA-assisted debug
- Demonstrated technical leadership
- Ability to influence verification quality beyond immediate ownership
- BS/MS Degree in EE, CE or CS
- 8+ years relevant experience with IP/Component functional verification
- Deep understand of computer architecture
- Seasoned developer using object oriented programing principles
- Successful background and reference checks
- Satisfactory proof of your right to work in United States of America
- Authorized for access to export-controlled technology under applicable export control laws
- Ability to successfully obtain any necessary export license(s) or other approvals
Desired Qualifications
- Experience verifying coherent interconnect, cache, or memory-subsystem IP in high-performance SoCs
- Experience with protocol-conversion or bridge-heavy subsystems
- Experience with formal verification
- Experience with performance-oriented verification
- Experience with emulation / FPGA-assisted debug
- Demonstrated technical leadership
- Ability to influence verification quality beyond immediate ownership
- Deep understand of computer architecture is desired
- Seasoned developer using object oriented programing principles
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