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Marvell TechnologyPosted 3 weeks ago

Senior Staff Design Engineer - Memory Subsystem COE

$135,900–$201,130 year

On-siteSan Diego, California, United States

Full TimeSenior LevelDoctorate Or Professional DegreeLarge

Job Summary

Own and drive DDR/LPDDR/HBM subsystem micro-architecture definition, RTL implementation, and integration for Marvell's custom chips powering hyperscale cloud and AI customers. Collaborate with Architecture teams to translate requirements into robust designs, partner with verification and physical design groups to ensure DFT-ready RTL, and support silicon bring-up and post-silicon debug with firmware and validation teams. Drive design quality improvements, coding best practices, and reuse across projects while mentoring junior designers and providing technical leadership within the DDR/LPDDR/HBM domain.

Required Qualifications

  • Bachelor's degree in Electronics/Electrical Engineering
  • 5-10+ years of relevant experience in RTL design
  • Master's and/or PhD with 3-5 yrs of relevant experience
  • Proven experience delivering complex DDR, LPDDR, HBM controllers or subsystems from architecture through RTL closure
  • Strong hands-on experience in System Verilog / Verilog RTL development
  • Expertise/Familiarity in DDR/HBM JEDEC specifications
  • Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE)
  • Solid grasp of Clocking, Resets, CDC/RDC, low-power techniques, and performance optimization
  • Experience supporting lint, CDC/RDC, synthesis, and design sign-off flows
  • Experience using industry-standard EDA tools from Synopsys, Cadence, Mentor/Siemens
  • Proficient in scripting languages such as TCL / Perl / Python
  • Experience with version control systems such as GIT, SVN, etc.

Desired Qualifications

  • Experience on end-to-end DDR/HBM subsystem RTL design execution and sign-off
  • Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms
  • Proficient in debugging functional and performance issues at subsystem and SoC levels
  • Familiarity with post-silicon bring-up and debug methodologies in collaboration with firmware and validation teams
  • Prior experience mentoring engineers and providing technical leadership in a cross-functional environment

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