Senior Staff Design Engineer, IC Layout
$158,700–$238,100 year
RemoteUnited States or Seattle, Washington, United States
Job Summary
Leverage Top-Down Bottom-Up floorplan methodology to create and refine RFID or Reader IC floorplans, collaborating with circuit and block-level layout designers on sizing, pin rings, and inter-block routing. Work closely with analog and digital design teams on power supply strategy and signal distribution, then coordinate with program managers and cross-functional partners to track activities to a predictable schedule and lead successful tape-outs. Conduct layout reviews for power/ground routing, electromigration, matching, and signal integrity, completing full-chip closure activities including seal-ring integration, dummy fill, DRC, LVS, density, and DFM checks. Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for high-performance and ultra-low power applications while participating in the IC layout methodology roadmap.
Required Qualifications
- Bachelor's or master's degree in computer or electrical engineering or a related technical field
- 12+ years of experience
- Experience in custom analog, RF, and mixed-signal layout
- Ability to lead complex ICs from conception to tapeout
- Versed in tapeout flows with experience in final database preparation and tapeout checklists
- Ability to lead and mentor other layout engineers as the top-level floorplan/IC integration owner
- Expert in full-chip/SOC-level floorplanning and integration
- Expert knowledge of Cadence Virtuoso schematic and layout editors
- Expert knowledge of Cadence/Siemens layout verification tools (including PVS and Siemens Calibre DRC/LVS)
- Strong proficiency interpreting and correcting ERC, DRC and LVS error reports
- Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm
- Understanding of analog layout challenges and layout-dependent effects in advanced processes
- Expert knowledge of guard rings, DNW, PN junctions, parasitic management, signal integrity, reliability (EMIR), and ESD
- Demonstrated strong technical project management skills with the ability to prioritize tasks, anticipate roadblocks, manage schedules, and deliver results in a fast-paced environment
Desired Qualifications
- Experience with AOT and DOT methodologies
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