Senior Staff ASIC Design Engineer

Senior Staff ASIC Design Engineer responsible for the design and implementation/integration of SoCs. Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks. Support prototyping, test program development, chip validation, and chip life until production maturity. Collaborate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout ASIC development. Must have 12+ years of experience in RTL logic design, verification, synthesis, and timing optimization; proficient in Verilog and SoC integration; strong understanding of assertions, coverage analysis, RTL synthesis, and timing closure; experience with PCIe, USB, Ethernet, DDR4/5, I2C/I3C, eSPI, SPI; experience in design bring up on FPGA-based emulation platforms like HAPS/Veloce; scripting with Perl/Python; must have completed at least one tape-out cycle; preferred silicon bring-up and debug experience; experience with Bitbucket/Jenkins and JIRA. Axiado is headquartered in Silicon Valley and is an Equal Opportunity Employer.