Senior STA engineer

Senior Digital Design Engineer leading block-level digital design synthesis and STA efforts. Manages timing closure, power optimization, and mentors junior engineers. Requires hands-on experience in Digital Synthesis, DFT insertion, Check Design and Check Timing Analysis; strong understanding of liberty models including power; capable of developing complex timing constraints for blocks and full-chip, and performing timing analysis and signoff for high-speed SoC designs (16nm and below). Proficient in RTL to GDS flows, Tcl/Perl/Python scripting for automation, and physical design activities (Floorplanning, CTS, Routing, Extraction, PV). Strong collaboration and communication skills; experienced with SCAN/DFT, ECOs, and timing-DRC issues; familiarity with OSS of EDA tools and high-speed timing signoff. Preferred Education and Experience: Bachelor's or Master's degree in Electrical/Computer Engineering or equivalent, 4-6 years in Synthesis and STA.