Senior SRAM Layout Design Engineer

Senior SRAM Layout Design Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. Build custom memory layouts from initial floorplanning through DRC/LVS-clean tapeout, collaborating with circuit design, physical design, integration, CAD, and foundry teams. Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros; develop floorplans for SRAM and memory blocks including array layout, periphery positioning, power grid design, routing channels, and macro assembly. Perform DRC, LVS, ERC, antenna, and related physical verification checks using tools such as Calibre/ICV; support EM/IR review, power integrity, density/fill, DFM, dummy insertion, and tapeout requirements. Ensure matching, symmetry, shielding, parasitic targets, and reliability constraints in collaboration with circuit designers; resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues with PnR/integration teams. Advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery; work with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and process constraints. Review layouts, mentor junior engineers, and raise layout quality across the team. Ways to stand out: Cadence SKILL/Python scripting for automation and workflow improvements; strong familiarity with EM/IR, reliability, density, fill, DFM, and post-processing at IP/top levels. Base salary ranges are provided with equity/benefits; posting notes that NVIDIA is an equal opportunity employer and that applications are accepted until a specified date.