Senior SoC Compute/Memory Subsystem Architect

Senior SoC Compute/Memory Subsystem Architect to define and drive end-to-end architecture for compute complexes and high-performance memory subsystems in IPU/DPU platforms. Responsibilities include defining architecture for IPU compute complexes (core selection, scaling, configuration tradeoffs); architecting compute subsystem roles (control plane, data plane, offload execution, management services); designing multi-level cache hierarchies and coherency models across compute cores, accelerators, and IO subsystems; architecting system memory subsystems (DDR/LPDDR interfaces, memory controllers, bandwidth strategies); collaborating on IO memory virtualization (SMMU/IOMMU) with multi-tenant isolation and security boundaries; system-level integration across compute, network, storage, and accelerator subsystems; and defining power efficiency and scaling strategies, roadmap for multi-generation evolution, and cross-functional leadership with networking, firmware/os, validation, and performance teams. The role emphasizes long-term architecture vision, technical leadership, and collaboration in a hybrid on-site/off-site work model in multiple US locations.