Senior SoC Architect
$170,500–$315,490 year
Hybrid · Santa Clara, California, United States
Job Summary
Senior architect lead to define and drive architecture specifications for Unified Intel Chassis IP components and subsystems; ensure architecture is implementation-aware, scalable, and power-optimized; drive platform performance analysis and closure; build and enhance performance environments, models, and benchmarking flows; define end-to-end QoS, arbitration, and routing strategies for high-bandwidth traffic; collaborate with system architects, RTL/design, verification, firmware/software, and performance teams to align architecture with product goals; support debuggability, safety, reliability, and serviceability in architecture definition; UIC IP scope includes coherent/non-coherent fabric, MMU/IOMMU, clock/power management, security/ access management; minimum qualifications include a Bachelor’s degree with 6+ years or MS with 4+ years of relevant experience; role supports a hybrid work model in the US.
Required Qualifications
- Bachelor’s degree in Computer Science, Electrical Engineering, or related discipline OR MS degree in Computer Science, Electrical Engineering, or related discipline with 4+ years of relevant experience
Desired Qualifications
- Experience in SoC IP architecture for high bandwidth interconnect and/or subsystem design
- Writing high-quality architecture specifications used by design and verification teams
- Power optimization techniques
- Arbitration and routing algorithms, QoS, high-bandwidth low-latency design
- Experience with AXI, CHI, APB, AMBA protocols
- Collaboration across architecture and implementation teams
- Debug, safety, and RAS architecture understanding
- Fabric-based scalable platforms experience
- Performance modelling, simulation, and data-driven architecture tuning
- Memory management and MMU/IOMMU knowledge
- Security architecture and access control in SoC platforms
- DVFS and distributed power management
- Experience with end-to-end platform performance environments and benchmarking
- Anchor architecture requirements, interfaces, and trade-offs
- Experience with cross-generation product architectures
- Experience with Spec2Silicon or machine-readable specification tools (preferred)
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