Senior SoC Architect (f/m/d)
RemoteGermany
Job Summary
Own the overall EPIC SoC technical leadership from initial concept through production, translating Marketing Requirement Documents into complete, implementable Product Requirement Documents covering digital, analog, I/O, and memory subsystems. Drive full-chip performance, power, and area trade-off analysis while partnering with external vendors on validation and characterization. Present the integrated architecture and PRD to product management and engineering leadership for sign-off. This role requires 7–10 years of SoC or product architecture experience with deep expertise in high-speed SerDes and protocols including UCIe, PCIe, and Ethernet. Full-time employment is available in the semiconductor industry, where graphene solutions are transforming high-throughput, low-delay computing networks.
Required Qualifications
- 7–10 years of experience in SoC or product architecture roles
- proven SoC/product architecture ownership
- demonstrated experience taking a product from MRD-level requirements through a complete, implementable PRD-level architecture
- experience covering multiple subsystems
- experience with at least one full product architecture cycle
- Deep, hands-on high-speed I/O subsystem expertise
- expertise in high-speed SerDes
- knowledge of protocol digital logic for UCIe
- knowledge of protocol digital logic for PCIe
- knowledge of protocol digital logic for Ethernet
- ability to explain how protocol requirements shape physical-layer architecture
- Strong digital subsystem and interconnect fabric architecture experience
- experience defining on-chip interconnect
- experience with digital subsystem partitioning
- experience for a complex SoC
- Strong cross-domain integration skills
- ability to take analog architecture input from peer subsystem owners
- ability to take photonic architecture input from peer subsystem owners
- ability to take packaging architecture input from peer subsystem owners
- ability to take memory architecture input from peer subsystem owners
- ability to integrate input into one internally consistent PRD
- ability to do this without needing to personally own those domains
- Experience translating marketing/product-level requirements into precise, engineering-actionable architecture specifications
- experience reasoning about full-chip performance, power, and area (PPA) trade-offs
- Experience with 3rd-party IP vendors
- experience evaluating and selecting external IPs
- experience with design integration partners
- Experience with architecture specification and requirements management tooling
- experience authoring and maintaining the PRD
- experience tracing it back to the MRD
- knowledge of UCIe protocol/standards documentation and compliance tooling
- knowledge of PCIe protocol/standards documentation and compliance tooling
- knowledge of Ethernet protocol/standards documentation and compliance tooling
- experience with architecture and performance modeling tools
- experience with custom or commercial full-chip performance/power models
- knowledge of Python for modeling, scripting, and analysis
- knowledge of C++ for modeling, scripting, and analysis
- knowledge of collaboration and documentation platforms
- ability to coordinate input from analog, photonics, packaging, memory, and other subsystem architects into a single PRD
Desired Qualifications
- Previous experience serving as an SoC Chief Engineer
- end-to-end accountability for a product's full-chip architecture
- accountability for a product's schedule
- accountability for a product's quality outcomes
- Familiarity with silicon photonics or electro-optic I/O
- knowledge of how it changes traditional I/O subsystem architecture assumptions
- Familiarity with advanced packaging
- knowledge of 2.5D/3D and chiplet integration
- knowledge of its impact on full-chip architecture choices
- Experience working directly with product management and/or customers to shape MRD-level requirements
- Experience with CXL
- knowledge of other die-to-die/coherent interconnect standards
- knowledge adjacent to UCIe/PCIe
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