Senior Principal Engineer (PE) / Subject Matter Expert (SME) – Quartus Timing Analysis & Optimization
$266,200–$392,200 year
On-siteSan Jose, California, United States
Job Summary
Define the technical roadmap for timing analysis, modeling, and optimization within the Quartus FPGA Compiler. Architect next-generation Static Timing Analysis capabilities, including multi-corner multi-mode analysis and clock domain crossing scenarios. Develop methodologies to improve timing convergence across the RTL-to-bitstream flow while maintaining industry-leading scalability. Design scalable algorithms for compiler performance through parallelization and incremental processing. Partner with architecture, synthesis, and routing teams to drive innovations in delay modeling and signoff correlation. Provide technical mentorship and influence future FPGA compiler capabilities through long-term strategic planning.
Required Qualifications
- MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or related field
- 15+ years of experience in EDA software development, timing analysis, physical design, FPGA compilation, or related domains
- Deep expertise in: Static Timing Analysis (STA)
- Deep expertise in: Timing closure methodologies
- Deep expertise in: Timing modeling and correlation
- Deep expertise in: Physical design optimization
- Deep expertise in: RTL-to-GDS or RTL-to-bitstream design flows
- Deep expertise in: Multi-corner multi-mode (MCMM) analysis
- Strong understanding of: Placement and routing algorithms
- Strong understanding of: Clock analysis and optimization
- Strong understanding of: Path-Based Analysis (PBA)
- Strong understanding of: Constraint management and timing exceptions
- Strong understanding of: Incremental timing architectures
- Extensive software development experience in C++ and large-scale optimization systems
- Proven track record developing high-performance, highly scalable EDA engines
- Applicants must be eligible for any required U.S. export authorizations
- Must be eligible for any required U.S. export authorizations
Desired Qualifications
- Direct experience developing FPGA compilation tools
- Prior experience with the Quartus compiler, Timing Analyzer, Fitter, Routing, or related FPGA implementation technologies
- Expertise in one or more of the following: Path-based timing optimization
- Expertise in one or more of the following: Clock-Reconvergence Pessimism Removal (CRPR)
- Expertise in one or more of the following: Latch-based timing analysis
- Expertise in one or more of the following: Incremental optimization frameworks
- Expertise in one or more of the following: Timing-driven placement and routing
- Expertise in one or more of the following: Variation-aware analysis techniques
- Experience designing multi-threaded or distributed EDA infrastructure
- Industry-recognized technical leadership demonstrated through patents, publications, standards contributions, or major product innovations
- Recognized subject matter expertise in timing analysis and optimization
- Ability to drive complex technical initiatives from concept to production
- Strong systems-thinking approach to compiler architecture and optimization
- Passion for solving challenging timing closure and scalability problems
- Proven ability to influence engineering direction across multiple organizations
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