Senior Principal Engineer PD
On-siteSingapore, Singapore
Job Summary
Conduct block-level and top-level physical implementation including floorplanning, placement, clock tree synthesis, routing, and physical verification for high-speed designs targeting TSMC 3nm and advanced nodes. Collaborate with RTL and STA teams to ensure timing, area, and power convergence while applying advanced techniques for multiple voltage and frequency domains. Execute EM/IR analysis, congestion mitigation, and clock skew optimization using industry-standard tools such as ICC2, Innovus, Voltus, RedHawk, and Calibre. Develop automation scripts in Tcl, Python, or Perl to enhance physical design flows and productivity. Support ECO implementation and tapeout signoff activities, ensuring clean DRC, LVS, ANT, CELL, and ERC databases. Integrate high-speed IPs and top-level blocks with attention to physical interfaces and timing alignment.
Required Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field
- 5+ years of experience in physical design, preferably with advanced technology nodes
- Strong experience with: Floorplanning, placement, CTS, routing, and IR drop mitigation
- Signoff checks such as DRC, LVS, ANT, and ERC, along with debugging
- Timing closure support in collaboration with STA teams
- Hands-on use of tools such as Synopsys ICC2, Cadence Innovus, Calibre, and Voltus
- Experience integrating high-speed IPs such as SerDes or PHYs into SoC or chiplet-based environments
- Experience working on high-frequency datapath and DSP-related designs
- Solid scripting skills for automation and productivity enhancement
- Good problem-solving skills and the ability to work effectively in cross-functional teams
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