Senior Principal Engineer - IP Verification

Senior Principal Engineer - IP Verification responsible for driving end-to-end IP/Subsystem verification using HVLs (UVM/SystemVerilog/C++), conducting testbench and testplan development, and integrating verification across global teams. Focus areas include complex IPs/subsystems, formal verification, pre-silicon validation, and leveraging verification methodologies to deliver high-quality, defect-free designs. Experience with ARM cores, AMBA/AXI, memory controllers, Ethernet, automotive graphics/vision accelerators, and end-to-end verification cycles is required; strong collaboration with multi-site teams and stakeholders is expected.