Senior Principal Engineer- HBM PHY

Senior Principal Logic Architect to lead the architecture and execution of next-generation HBM PHY solutions for AI, HPC, and hyperscale systems. This high-impact individual-contributor leadership role covers end-to-end ownership across architecture, microarchitecture, and silicon delivery, with responsibilities including translating system requirements into architecture specifications, guiding RTL implementation, and driving HBM4 roadmap decisions. The role requires collaboration with analog/mixed-signal teams, SoC architects, packaging, SI/PI, RTL, DV, firmware, and validation; ownership of post-silicon bring-up and root-cause analysis; and influence on industry standards (e.g., JEDEC). The candidate should possess deep expertise in HBM PHY or high-speed interfaces, strong system-level trade-off skills (PPA, SI/PI, packaging interactions), and demonstrated leadership to mentor and elevate engineering teams. Preferred experience with HBM3/HBM4, memory architectures, AI/ML accelerators or hyperscale SoCs, and advanced packaging (2.5D/3D, chiplets, interposers). The role offers high visibility and broad technical ownership in shaping next-generation memory architecture for AI/HPC platforms at scale.