Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity
$177,820–$266,400 year
On-site · Santa Clara, California, United States
Job Summary
Senior Principal Engineer for Signal Integrity and Power Integrity leading technical authority for customer platforms built on Marvell's Ethernet Switch and UALink silicon. Define and maintain layout and routing guidelines for high-speed SerDes channels and power delivery networks; perform post-silicon channel extraction, full-channel simulations, and what-if analysis; lead compliance testing (BER/SER, eye margins, jitter, return loss, crosstalk) and translate measurements into SerDes tuning guidance. Provide PDN simulations (impedance, IR drop, decoupling, transient response, droop) and guide robust PDN architectures. Engage with ODMs on SI/PI guidance, design reviews, and qualification activities; support reference design definitions from early channel budgeting to customer release. Deliver hands-on lab debug with VNAs, BERTs, scopes, TDRs, and jitter analyzers; develop SI/PI training for customers, ODMs, and internal teams. Lead technical leadership on 112G and 224G PAM4 SerDes designs and shape approaches for 448G systems. Travel to customer sites as needed. Participate in architecture discussions, roadmap inputs, and represent Marvell’s hardware expertise in customer briefings and industry forums.
Required Qualifications
- 15+ years hardware design experience for high-speed networking/compute systems
- 10+ years focused SI/PI on high-speed SerDes (25G NRZ through 112G/224G PAM4)
- expertise in channel modeling, layout guideline definition, post-layout extraction and simulation
- ability to run PDN simulations (impedance, IR drop, decoupling, transient response, droop) and translate results to guidance
- strong hands-on lab skills with VNAs, BERTs, oscilloscopes, TDR, jitter analyzers, compliance test kits
- customer-facing experience and ability to train engineering audiences
- excellent communication to influence customers, ODMs, and internal stakeholders
- travel willingness for customer sites, ODMs, and labs
- experience with Ethernet switch platforms and emerging open AI fabric standards (preferred)
- experience enabling silicon-based solutions with ODM/CM flows and high-volume manufacturing variability
- familiarity with SerDes tuning methodologies and correlating simulations with lab/field telemetry
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