Senior Principal Design Engineer
On-site · Austin, Texas, United States or San Jose, California, United States
Job Summary
Senior Principal Design Engineer focused on RTL-to-GDSII delivery, owning block and top-level implementation and signoff efforts, with expertise in Verilog ASIC design, Synthesis/PnR/CTS/STA, and Cadence/Synopsys toolchains; role involves customer evaluations, methodology development, and collaboration across multiple tech nodes, including potential involvement in competitive benchmarking and design tapeouts; requires strong communication for technical presentations and demonstrations; located in Austin or San Jose, US.
Required Qualifications
- BS degree in a relevant field
- 7 years of experience in design engineering or equivalent
- ASIC design experience with Verilog
- Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis)
- Experience with RTL-to-GDSII workflows and Encounter Digital Implementation Platform
- Ability to support RTL-to-GDS tapeouts and provide methodology
- Experience with Low Power and Multi-Voltage Design techniques
- Ability to create technical presentations and product demonstrations
- Familiarity with Synthesis with Genus, DFT & Scan with Encounter Test (ET)
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