Senior Principal ASIC FPGA Engineer
HybridBoise, Idaho, United States
Boise, Idaho, United StatesHybridFull TimeSenior LevelMasters DegreeLarge
Full TimeSenior LevelMasters DegreeLarge
Job Summary
Own the architecture for ASIC/FPGA designs from concept through silicon, defining system partitioning, microarchitecture, and interface requirements. Drive RTL development with a focus on correctness, managing bus fabric integrity, clock domain crossings, and reset sequencing. Navigate synthesis, place and route, and static timing analysis to meet timing in advanced process nodes, fixing root causes rather than just running tools. Lead verification by developing test plans, driving closure on failures, and serving as the primary contact for functional criteria. Manage JIRA triage, prioritize backlog items, and contribute to Integrated Master Schedule development and earned value reporting. Conduct code reviews, guide technology selection for foundries and EDA tools, and support large proposals and subcontracts. Mentor engineers and collaborate across multi-divisional product teams.
Required Qualifications
- Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field
- Minimum of 10 years of relevant experience
- Master's degree
- Minimum of 8 years of relevant experience
- Department of Defense Secret security clearance
- U.S. Government security investigation eligibility
- Eligibility requirements for access to classified information
- U.S. citizenship
- 10–15+ years of ASIC/FPGA design experience
- Majority of experience spent as an RTL designer
- Proven experience taking designs through full ASIC tape-out
- Deep familiarity with FinFET process nodes (7nm, 5nm, or similar)
- Experience with commercial foundry flows (TSMC, GlobalFoundries, Samsung, or equivalent)
- Expert-level understanding of ASIC/FPGA engineering concepts
- Expert-level understanding of RTL coding practices
- Expert-level understanding of synthesis flows
- Strong familiarity with industry-standard EDA tools (synthesis, simulation, formal verification, STA)
- Demonstrated ability to operate independently
- Proficiency in JIRA for issue tracking and backlog management
- Proficiency in Microsoft Office for documentation and communication
Desired Qualifications
- Experience with timing closure under pressure
- Experience untangling bus fabric correctness issues
- Experience debugging reset sequencing nightmares
- Experience bringing complex silicon to tape-out
- Having lived the full ASIC design lifecycle
- Thinking in architecture and microarchitecture first
- Understanding the downstream implications of every design decision
- Being a self-starter
- Operating with minimal supervision
- Taking ownership of their domain
- Driving progress independently
- Bringing solutions rather than waiting to be directed
- Leading from the front
- Experience running P&R tools
- RTL designer at heart
- Deep understanding of what it takes to meet timing in advanced process nodes
- Fixing timing problems rather than just running tools
- Serving as the primary point of contact for verification activities
- Developing and owning test and simulation plans
- Establishing rigorous functional criteria
- Verifying results and driving closure on failures
- Reviewing incoming issues
- Prioritizing work items
- Ensuring the backlog reflects program reality
- Conducting and leading RTL code reviews
- Setting the technical bar
- Providing actionable, constructive feedback to engineers at all levels
- Contributing to Integrated Master Schedule (IMS) development
- Providing accurate technical input on task status, completion criteria, and schedule risk
- High-level design through GDSII
- Understanding synthesis, P&R, timing, power analysis, and DFT considerations
- Assessing foundry technologies
- Assessing device libraries
- Assessing IP cores
- Assessing EDA tooling
- Informing design decisions
- Leading ASIC/FPGA technical approach on large proposals
- Serving as book boss on medium proposals
- Managing technical subcontracts
- Developing SOW
- Source selection
- Work product acceptance
- Mentoring junior and mid-level engineers
- Contributing to the development and improvement of organizational ASIC/FPGA design processes
- Participating in multi-divisional or multi-company Integrated Product Teams
- Participating in working groups
- Helping shape what we build
- Helping shape how we build it
- Helping shape what it takes to get it right
- Seeing a gap and filling it without being asked
- Understanding the nuances of FinFET vs. planar technology
- Root cause analysis and fixing timing issues
- Power analysis and optimization
- Track record of innovative technical contributions
- Shaping the approach rather than just executing to spec
- Solid understanding of organizational processes
- Applying processes pragmatically across a program lifecycle
- Schedule management
- Earned value inputs
- Technical latitude
- Program impact that shows up in new business
- Team that values engineers who know the difference between running the tools and knowing what the tools are telling you
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